SH7713 Datasheet, PDF(516/904 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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SH7713 Datasheet, PDF (516/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Section 13 Direct Memory Access Controller (DMAC)

Figure 13.2 is a flowchart of this procedure.

Start

Initial settings

(SAR, DAR, DMATCR, CHCR, DMAOR, DMARS)

DE, DME = 1 and

No

NMIF, AE, TE = 0?

Yes

Transfer request

No

occurs?*1

Yes

Transfer (1 transfer unit);

DMATCR â 1 â DMATCR, SAR and DAR

updated

*2

Bus mode,

*3

transfer request mode,

DREQ detection selection

system

No

DMATCR = 0?

Yes

TE = 1

DEI interrupt request (when IE = 1)

NMIF = 1

or AE = 1 or DE = 0

or DME = 0?

Yes

Transfer end

No

Normal end

NMIF = 1

No

or AE = 1 or DE = 0

or DME = 0?

Yes

Transfer aborted

Notes: *1 In auto-request mode, transfer begins when NMIF, AE and TE are all 0 and the DE and DME

bits are set to 1.

*2 DREQ = level detection in burst mode (external request) or cycle-steal mode.

*3 DREQ = edge detection in burst mode (external request), or auto-request mode in burst mode.

Figure 13.2 DMA Transfer Flowchart

Rev.1.50 Aug. 30, 2006 Page 476 of 860

REJ09B0288-0150

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