SH7713 Datasheet, PDF (505/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Direct Memory Access Controller (DMAC)
Bit
22
21 to
18
17
16
Initial
Bit Name Value R/W
TL
0
R/W

All 0 R
AM
0
R/W
AL
0
R/W
Description
Transfer End Level
Specifies the TEND signal output is high active or low
active.
This bit is valid only in CHCR0 and CHCR1.This bit is
reserved and always read as 0 in CHCR2 to CHCR5. The
write value should always be 0.
0: Low-active output of TEND
1: High-active output of TEND
Reserved
These bits are always read as 0. The write value should
always be 0.
Acknowledge Mode
Specifies whether the DACK is output in data read cycle or
in data write cycle in dual address mode.
In single address mode, the DACK is always output
regardless of the specification by this bit.
This bit is valid only in CHCR0 and CHCR1.This bit is
reserved and always read as 0 in CHCR2 to CHCR5. The
write value should always be 0.
0: DACK output in read cycle (Dual address mode)
1: DACK output in write cycle (Dual address mode)
Acknowledge Level
Specifies the DACK signal output is high active or low
active.
This bit is valid only in CHCR0 and CHCR1.This bit is
reserved and always read as 0 in CHCR2 to CHCR5. The
write value should always be 0.
0: Low-active output of DACK
1: High-active output of DACK
Rev.1.50 Aug. 30, 2006 Page 465 of 860
REJ09B0288-0150