SH7713 Datasheet, PDF (532/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Direct Memory Access Controller (DMAC)
CKIO
Address
CS
RD
T1 T2 Taw T1 T2
Data
WEn
DACKn
(Active low)
TENDn
(Active low)
WAIT
Note: TEND is asserted for the last transfer unit of DMA transfers.
If a transfer unit is divided into multiple bus cycles and
if CS is negated during the bus cycle, TEND is also divided.
Figure 13.17 Example of BSC Ordinary Memory Access
(No Wait, Idle Cycle = 1, Longword Access to 16-bit Device)
Rev.1.50 Aug. 30, 2006 Page 492 of 860
REJ09B0288-0150