SH7713 Datasheet, PDF (723/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
Bit
Bit Name Value R/W Description
7
RMAFIP 0
R/W Receive Multicast Address Frame Interrupt Enable
0: Receive multicast address frame interrupt is disabled
1: Receive multicast address frame interrupt is enabled
6, 5

All 0
R Reserved
These bits are always read as 0. The write value
should always be 0.
4
RRFIP
0
R/W Receive Residual-Bit Frame Interrupt Enable
0: Receive residual-bit frame interrupt is disabled
1: Receive residual-bit frame interrupt is enabled
3
RTLFIP
0
R/W Receive Too-Long Frame Interrupt Enable
0: Receive too-long frame interrupt is disabled
1: Receive too-long frame interrupt is enabled
2
RTSFIP
0
R/W Receive Too-Short Frame Interrupt Enable
0: Receive too-short frame interrupt is disabled
1: Receive too-short frame interrupt is enabled
1
PREIP
0
R/W PHY-LSI Receive Error Interrupt Enable
0: PHY-LSI receive error interrupt is disabled
1: PHY-LSI receive error interrupt is enabled
0
CERFIP 0
R/W ^{CRC Error on Received Frame}
0: CRC error on received frame interrupt is disabled
1: CRC error on received frame interrupt is enabled
Rev.1.50 Aug. 30, 2006 Page 683 of 860
REJ09B0288-0150