SH7713 Datasheet, PDF (523/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Direct Memory Access Controller (DMAC)
DMAC
SAR
DAR
Memory
Transfer source
module
Data buffer
Transfer destination
module
The SAR value is an address, data is read from the transfer source module,
and the data is temporarily stored in the DMAC.
DMAC
First bus cycle
SAR
Memory
DAR
Transfer source
module
Data buffer
Transfer destination
module
The DAR value is an address and the value stored in the data buffer in the
DMAC is written to the transfer destination module.
Second bus cycle
Figure 13.5 Data Flow in Dual Address Mode
Auto request, external request, and on-chip peripheral module request are available for the
transfer request. DACK can be output in read cycle or write cycle in dual address mode. The
AM bit of the channel control register (CHCR) can specify whether the DACK is output in
read cycle or write cycle.
Figure 13.6 shows an example of DMA transfer timing in dual address mode.
Rev.1.50 Aug. 30, 2006 Page 483 of 860
REJ09B0288-0150