SH7713 Datasheet, PDF (487/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
12.5.8 PCMCIA Interface
With this LSI, if address map (2) is selected using the MAP bit in CMNCR, the PCMCIA
interface can be specified in areas 5 and 6. Areas 5 and 6 in the physical space can be used for the
IC memory card and I/O card interface defined in the JEIDA specifications version 4.2
(PCMCIA2.1 Rev. 2.1) by specifying the TYPE[3:0] bits of CSnBCR (n = 5B, 6B) to B’0101. In
addition, the SA[1:0] bits of CSnWCR (n = 5B, 6B) assign the upper or lower 32 Mbytes of each
area to an IC memory card or I/O card interface. For example, if the SA1 and SA0 bits of the
CS5BWCR are set to 1 and cleared to 0, respectively, the upper 32 Mbytes and the lower 32
Mbytes of area 5B are used as an IC memory card interface and I/O card interface, respectively.
When the PCMCIA interface is used, the bus size must be specified as 8 bits or 16 bits using the
BSZ[1:0] bits in CS5BBCR or CS6BBCR.
Figure 12.38 shows an example of a connection between this LSI and the PCMCIA card. To
enable insertion and removal of the PCMCIA card during system power-on, a three-state buffer
must be connected between the LSI and the PCMCIA card.
In the JEIDA and PCMCIA standards, operation in the big endian mode is not clearly defined.
Consequently, an original definition is provided for the PCMCIA interface in big endian mode in
this LSI.
Rev.1.50 Aug. 30, 2006 Page 447 of 860
REJ09B0288-0150