SH7713 Datasheet, PDF (696/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
18.3.25 Receive Frame Counter Register (Normal and Error Reception) (RXALCR)
RXALCR is a 32-bit counter indicating the number of frames successfully received and frames
received with error in MAC. When the value in this register reaches H'FFFFFFFF, the count is
halted. The counter value is cleared to 0 by a read to this register. This register cannot be written.
Initial
Bit
Bit Name Value
31 to 0 RC031 to All 0
RC000
R/W Description
R
Receive Frame Counter Bit
These bits indicate the number of frames successfully
received and frames received with error.
18.4 Operation
The following outlines the operations of the Ethernet controller (EtherC).
18.4.1 Transmission
The EtherC transmitter assembles the transmit data on the frame and outputs to MII when there is
a transmit request from the E-DMAC. The data transmitted via the MII is transmitted to the lines
by PHY-LSI. Figure 18.2 shows the status change of the Ether-C transmitter.
Rev.1.50 Aug. 30, 2006 Page 656 of 860
REJ09B0288-0150