SH7713 Datasheet, PDF (265/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 6 Cache
PA (31 to 4) Longword 0 Longword 1 Longword 2 Longword 3
PA (31 to 4):
Physical address written to external memory
Longword 0 to 3: One line of cache data to be written to external
memory
Figure 6.3 Write-Back Buffer Configuration
6.3.6 Coherency of Cache and External Memory
Use software to ensure coherency between the cache and the external memory. When memory
shared by this LSI and another device is placed in an address space to which caching applies, use
the memory-mapped cache to make the data invalid and written back, as required. Memory that is
shared by this LSI’s CPU and DMAC should also be handled in this way.
Rev.1.50 Aug. 30, 2006 Page 225 of 860
REJ09B0288-0150