SH7713 Datasheet, PDF (93/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Type
Arithmetic
operation
instructions
Logic
operation
instructions
Shift
instructions
Kinds of
Instruction
21
Op Code
MAC
MUL
MULS
MULU
NEG
NEGC
SUB
SUBC
SUBV
6
AND
NOT
OR
TAS
TST
XOR
12
ROTL
ROTR
ROTCL
ROTCR
SHAL
SHAR
SHLL
SHLLn
SHLR
SHLRn
SHAD
SHLD
Function
Multiply-and-accumulate, double-
precision multiply-and-accumulate
Double-precision multiplication
(32 × 32 bits)
Signed multiplication (16 × 16 bits)
Unsigned multiplication (16 × 16 bits)
Sign inversion
Sign inversion with borrow
Binary subtraction
Binary subtraction with carry
Binary subtraction with underflow
Logical AND
Bit inversion
Logical OR
Memory test and bit setting
Logical AND and T bit setting
Exclusive logical OR
1-bit left shift
1-bit right shift
1-bit left shift with T bit
1-bit right shift with T bit
Arithmetic 1-bit left shift
Arithmetic 1-bit right shift
Logical 1-bit left shift
Logical n-bit left shift
Logical 1-bit right shift
Logical n-bit right shift
Arithmetic dynamic shift
Logical dynamic shift
Number of
Instructions
33
14
16
Rev.1.50 Aug. 30, 2006 Page 53 of 860
REJ09B0288-0150