SH7713 Datasheet, PDF (374/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
12.2 Input/Output Pins
The configuration of pins in this module is shown in table 12.1.
Table 12.1 Pin Configuration
Name
A25 to A0
D31 to D0
BS
CS0, CS2 to CS4
CS5A
CS5B/CE1A
CE2A
CS6A
CS6B/CE1B
CE2B
RD/WR
RD
I/O Function
O Address bus
I/O Data bus
O Bus cycle start
Asserted when a normal space, burst ROM (clock
synchronous/asynchronous), or PCMCIA is accessed. Asserted by the
same timing as CAS in SDRAM access.
O Chip select
O Chip select
Active only for address map 1
O Chip select
Corresponds to PCMCIA card select signals D7 to D0 when the
PCMCIA is used.
O Corresponds to PCMCIA card select signals D15 to D8 when the
PCMCIA is used.
O Chip select
Active only for address map 1
O Chip select
Corresponds to PCMCIA card select signals D7 to D0 when the
PCMCIA is used.
O Corresponds to PCMCIA card select signals D15 to D8 when the
PCMCIA is used.
O Read/write
Connects to WE pins when SDRAM or byte-selection SRAM is
connected.
O Read pulse signal (read data output enable signal)
A strobe signal to indicate the memory read cycle when the PCMCIA is
used.
Rev.1.50 Aug. 30, 2006 Page 334 of 860
REJ09B0288-0150