SH7713 Datasheet, PDF (750/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
19.3.3 Reception
When 1 is written to the receive request bit (RR) in the E-DMAC receive request register
(EDRRR) while the RE bit in ECMR is set to 1, the E-DMAC reads the descriptor following the
previously used descriptor from the receive descriptor list (or the descriptor indicated by the
receive descriptor start address register (RDLAR) at the initial start time) then enters the receive
standby state. When the EtherC receives a frame for this LSI (with an address enabled for
reception by this LSI), the EtherC stores the receive data in the receive FIFO. The receive data is
transferred to the receive buffer specified by RD2 according to the receive descriptor with the
RACT bit set to 1 (valid). If the data length of a received frame is longer than the buffer length
specified by RD1, the E-DMAC performs a write-back operation to the descriptor (with RFP set to
10 or 00) when the buffer becomes full, then reads the next descriptor. The E-DMAC then
continues to transfer data to the receive buffer specified by the new RD2. When frame reception is
completed, or if frame reception is suspended because of a certain kind of error, the E-DMAC
performs write-back to the relevant descriptor (with RFP set to 11 or 01), and then ends the
receive processing. The E-DMAC then reads the next descriptor and enters the receive standby
state again.
To receive frames continuously, the receive enable control bit (RNC) must be set to 1 in the
receive method control register (RMCR). The initial value is 0.
Rev.1.50 Aug. 30, 2006 Page 710 of 860
REJ09B0288-0150