SH7713 Datasheet, PDF (80/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Initial
Bit
Bit Name Value R/W Description
0
T

R/W T Bit
Indicates true or false for compare instructions or carry or
borrow occurrence for an operation instruction with carry
or borrow. This bit can be specified by the SETT and
CLRT instructions in user mode.
At reset, this bit is undefined. This bit is not affected in an
exception handling state.
Note: The M, Q, S, and T bits can be set/cleared by the user mode specific instructions. Other bits
can be read or written in privileged mode.
Save Status Register (SSR): The save status register (SSR) can be accessed only in privileged
mode. Before entering the exception, the contents of the SR register is stored in the SSR register.
At reset, the SSR initial value is undefined.
Save Program Counter (SPC): The save program counter (SPC) can be accessed only in
privileged mode. Before entering the exception, the contents of the PC is stored in the SPC. At
reset, the SPC initial value is undefined.
Global Base Register (GBR): The global base register (GBR) is referenced as a base register in
GBR indirect addressing mode. At reset, the GBR initial value is undefined.
Vector Base Register (VBR): The global base register (GBR) can be accessed only in privileged
mode. If a transition from reset state to exception handling state occurs, this register is referenced
as a base address. For details, refer to section 4, Exception Handling. At reset, the VBR is
initialized as H'00000000.
Figure 2.6 shows the control register configuration.
Rev.1.50 Aug. 30, 2006 Page 40 of 860
REJ09B0288-0150