SH7713 Datasheet, PDF (432/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
CKIO
T1
T2
Tnop
T1
T2
A25 to A0
CSn
RD/WR
Read
RD
D15 to D0
Write
WEn(BEn)
D15 to D0
BS
DACKn^*
WAIT
Note: * The waveform for DACKn is when active low is specified.
Figure 12.4 Continuous Access for Normal Space 1, Bus Width = 16 bits, Longword Access,
CSnWCR.WM Bit = 0 (Access Wait = 0, Cycle Wait = 0)
Rev.1.50 Aug. 30, 2006 Page 392 of 860
REJ09B0288-0150