SH7713 Datasheet, PDF (101/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Table 2.9 Shift Instructions
Instruction
ROTL Rn
ROTR Rn
ROTCL Rn
ROTCR Rn
SHAD Rm, Rn
SHAL
SHAR
SHLD
Rn
Rn
Rm, Rn
SHLL Rn
SHLR Rn
SHLL2 Rn
SHLR2 Rn
SHLL8 Rn
SHLR8 Rn
SHLL16 Rn
SHLR16 Rn
Instruction Code Operation
Privileged
Mode
Cycles T Bit
0100nnnn00000100 T←Rn←MSB

1
MSB
0100nnnn00000101 LSB→Rn→T

1
LSB
0100nnnn00100100 T←Rn←T

1
MSB
0100nnnn00100101 T→Rn→T

1
LSB
0100nnnnmmmm1100 Rm ≥ 0: Rn << Rm → Rn

Rm < 0: Rn >> Rm → [MSB →
Rn]
1

0100nnnn00100000 T←Rn←0

1
MSB
0100nnnn00100001 MSB→Rn→T

1
LSB
0100nnnnmmmm1101 Rm ≥ 0: Rn << Rm → Rn

Rm < 0: Rn >> Rm → [0 → Rn]
1

0100nnnn00000000 T←Rn←0

1
MSB
0100nnnn00000001 0→Rn→T

1
LSB
0100nnnn00001000 Rn<<2 → Rn

1

0100nnnn00001001 Rn>>2 → Rn

1

0100nnnn00011000 Rn<<8 → Rn

1

0100nnnn00011001 Rn>>8 → Rn

1

0100nnnn00101000 Rn<<16 → Rn

1

0100nnnn00101001 Rn>>16 → Rn

1

Rev.1.50 Aug. 30, 2006 Page 61 of 860
REJ09B0288-0150