SH7713 Datasheet, PDF (703/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
MII Register Access Procedure: The program accesses MII registers via the PHY interface
register (PIR). Access is implemented by a combination of 1-bit-unit data write, 1-bit-unit data
read, bus release, and independent bus release. Figure 18.6 shows the MII register access timing.
The timing will differ depending on the PHY-LSI type.
(1) Write to PHY interface
register
MMD = 1
MDO = write data
MDC = 0
(2) Write to PHY interface
register
MMD = 1
MDO = write data
MDC = 1
MDC
MDO
(1) (2)
(3)
1-bit data write timing
relationship
(3) Write to PHY interface
register
MMD = 1
MDO = write data
MDC = 0
Figure 18.6 (1) 1-Bit Data Write Flowchart
Rev.1.50 Aug. 30, 2006 Page 663 of 860
REJ09B0288-0150