SH7713 Datasheet, PDF(327/904 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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SH7713 Datasheet, PDF (327/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Section 9 User Break Controller

9.3.7 PC Trace

1. Setting PCTE in BRCR to 1 enables PC traces. When branch (branch instruction, and interrupt

exception) is generated, the branch source address and branch destination address are stored in

BRSR and BRDR, respectively.

2. The values stored in BRSR and BRDR are as given below due to the kind of branch.

ï£§ If a branch occurs due to a branch instruction, the address of the branch instruction is saved

in BRSR and the address of the branch destination instruction is saved in BRDR.

ï£§ If a branch occurs due to an interrupt or exception, the value saved in SPC due to exception

occurrence is saved in BRSR and the start address of the exception handling routine is

saved in BRDR.

When a repeat loop of the DSP extended function is used, control being transferred from the

repeat end instruction to the repeat start instruction is not recognized as a branch, and the

values are not stored in BRSR and BRDR.

3. BRSR and BRDR have eight pairs of queue structures. The top of queues is read first when the

address stored in the PC trace register is read. BRSR and BRDR share the read pointer. Read

BRSR and BRDR in order, the queue only shifts after BRDR is read. After switching the

PCTE bit (in BRCR) off and on, the values in the queues are invalid.

9.3.8 Usage Examples

Break Condition Specified for L Bus Instruction Fetch Cycle:

â¢ Register specifications

BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BARB = H'00008010,

BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000,

BRCR = H'00300400

Specified conditions: Channel A/channel B independent mode

<Channel A>

Address: H'00000404, Address mask: H'00000000

Bus cycle: L bus/instruction fetch (after instruction execution)/read (operand size is not

included in the condition)

The ASID check is not included.

<Channel B>

Address: H'00008010, Address mask: H'00000006

Data:

H'00000000, Data mask: H'00000000

Rev.1.50 Aug. 30, 2006 Page 287 of 860

REJ09B0288-0150

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