SH7713 Datasheet, PDF (74/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
31
0 31
0 31
0
R0_BANK0^*1,*2
R1_BANK0^*2
R0_BANK1^*1,*3
R1_BANK1^*3
R0_BANK0^*1,*4
R1_BANK0^*4
R2_BANK0^*2
R3_BANK0^*2
R4_BANK0^*2
R5_BANK0^*2
R2_BANK1^*3
R3_BANK1^*3
R4_BANK1^*3
R5_BANK1^*3
R2_BANK0^*4
R3_BANK0^*4
R4_BANK0^*4
R5_BANK0^*4
R6_BANK0^*2
R7_BANK0^*2
R6_BANK1^*3
R7_BANK1^*3
R6_BANK0^*4
R7_BANK0^*4
R8
R8
R8
R9
R9
R9
R10
R10
R10
R11
R11
R11
R12
R12
R12
R13
R13
R13
R14
R14
R14
R15
R15
R15
SR
GBR
MACH
MACL
PR
PC
(a) User mode register
configuration
SR
SSR
GBR
MACH
MACL
PR
VBR
PC
SPC
R0_BANK0^*1,*4
R1_BANK0^*4
R2_BANK0^*4
R3_BANK0^*4
R4_BANK0^*4
R5_BANK0^*4
R6_BANK0^*4
R7_BANK0^*4
(b) Privileged mode register
configuration (RB = 1)
SR
SSR
GBR
MACH
MACL
PR
VBR
PC
SPC
R0_BANK1^*1,*3
R1_BANK1^*3
R2_BANK1^*3
R3_BANK1^*3
R4_BANK1^*3
R5_BANK1^*3
R6_BANK1^*3
R7_BANK1^*3
(c) Privileged mode register
configuration (RB = 0)
Notes: *1 The R0 register is used as an index register in indexed register indirect addressing mode
and indexed GBR indirect addressing mode.
*2 Bank register
*3 Bank register
Accessed as a general register when the RB bit is set to 1 in the SR register.
Accessed only by LDC/STC instructions when the RB bit is cleared to 0.
*4 Bank register
Accessed as a general register when the RB bit is cleared to 0 in the SR register.
Accessed only by LDC/STC instructions when the RB bit is set to 1.
Figure 2.3 Register Configuration in Each Processing Mode
Rev.1.50 Aug. 30, 2006 Page 34 of 860
REJ09B0288-0150