SH7713 Datasheet, PDF (272/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 7 X/Y Memory
• Priority order
In the event of simultaneous accesses to the same page from different buses, the accesses are
processed according to the priority order. The priority order is: I bus > X bus > L bus in the X
memory and I bus > Y bus > L bus in the Y memory.
7.2 Operation
7.2.1 Access from CPU
Methods for accessing by the CPU are directly via the L bus from the logical addresses, and via
the I bus after the logical addresses are converted to be the physical addresses using the MMU. As
long as a conflict on the page does not occur, access via the L bus is performed in one cycle.
Several cycles are necessary for accessing via the I bus. According to the CPU operating mode,
access from the CPU is as follows:
Privileged mode and privileged DSP mode (SR. MD = 1): The X/Y memory can be accessed by
the CPU directly from space P2. The MMU can be used to map the logical addresses in spaces P0
and P3 to this memory.
User DSP mode (SR.MD = 0 and SR.DSP = 1): The X/Y memory can be accessed by the CPU
directly from space Uxy. The MMU can be used to map the logical addresses in space U0 to this
memory.
User mode (SR.MD = 0 and SR.DSP = 0): The MMU can be used to map the logical addresses
in space U0 to this memory.
7.2.2 Access from DSP
Methods for accessing from the DSP differ according to instructions.
With a X data transfer instruction and a Y data transfer instruction, the X/Y memory is always
accessed via the X bus or Y bus. As long as a conflict on the page does not occur, access via the X
bus or Y bus is performed in one cycle. The X memory access via the X bus and the Y memory
access via the Y bus can be performed simultaneously.
In the case of a single data transfer instruction, methods for accessing from the DSP are directly
via the L bus from the logical addresses, and via the I bus after the logical addresses are converted
to be the physical addresses using the MMU. As long as a conflict on the page does not occur,
access via the L bus is performed in one cycle. Several cycles are necessary for accessing via the I
bus. According to the CPU operating mode, access from the CPU is as follows:
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