SH7713 Datasheet, PDF (436/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
12.5.3 Access Wait Control
Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to
WR0 in CSnWCR. It is possible for areas 4, 5A, and 5B to insert wait cycles independently in
read access and in write access. The areas other than 4, 5A, and 5B have common access wait for
read cycle and write cycle. The specified number of Tw cycles is inserted as wait cycles in a
normal space access shown in figure 12.9.
T1
Tw
T2
CKIO
A25 to A0
CSn
RD/WR
Read
RD
D31 to D0
Write
WEn(BEn)
D31 to D0
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 12.9 Wait Timing for Normal Space Access (Software Wait Only)
When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also
sampled. WAIT pin sampling is shown in figure 12.10. A 2-cycle wait is specified as a software
wait. The WAIT signal is sampled on the falling edge of CKIO at the transition from the T1 or Tw
cycle to the T2 cycle.
Rev.1.50 Aug. 30, 2006 Page 396 of 860
REJ09B0288-0150