SH7713 Datasheet, PDF (476/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Burst read/burst write (burst length 1):
Data Bus Width
16 bits
32 bits
CAS Latency
2
3
2
3
Access Address
H′A4FD5040
H′A4FD5060
H′A4FD5080
H′A4FD50C0
External Address Pin
H′0000040
H′0000060
H′0000080
H′00000C0
Mode register setting timing is shown in figure 12.29. A PALL command (all bank precharge
command) is firstly issued. A REF command (auto refresh command) is then issued 8 times. An
MRS command (mode register write command) is finally issued. Idle cycles, of which number is
specified by the TRP[1:0] bits in CSnWCR, are inserted between the PALL and the first REF. Idle
cycles, of which number is specified by the TRC[1:0]bits in CSnWCR, are inserted between REF
and REF, and between the 8th REF and MRS. Idle cycles, of which number is one or more, are
inserted between the MRS and a command to be issued next.
It is necessary to keep idle time of certain cycles for SDRAM before issuing PALL command after
power-on. Refer the manual of the SDRAM for the idle time to be needed. When the pulse width
of the reset signal is longer then the idle time, mode register setting can be started immediately
after the reset, but care should be taken when the pulse width of the reset signal is shorter than the
idle time.
Rev.1.50 Aug. 30, 2006 Page 436 of 860
REJ09B0288-0150