SH7713 Datasheet, PDF (443/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Setting
A2/3
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
11 (32 bits) 00 (11 bits) 00 (8 bits)
Output Pin of Row Address Column Address Synchronous DRAM
This LSI
Output
Output
Pin
Function
A1
A9
A1
Unused
A0
A8
A0
Example of connected memory
64-Mbit product (512 kwords x 32 bits x 4 banks, column 8 bits product): 1
16-Mbit product (512 kwords x 16 bits x 2 banks, column 8 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
3. If the number of 16-Mbit SDRAM (512 kwords × 16 bits × 2 banks: pin with 8-bit
column) is two, the bank address specification is not required. Therefore, the bank
address should be not used.
Rev.1.50 Aug. 30, 2006 Page 403 of 860
REJ09B0288-0150