SH7713 Datasheet, PDF (203/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 4 Exception Handling
Table 4.1 Exception Event Vectors
Current
Exception Type Instruction Exception Event
Exception Process Vector
Priority*¹ Order
at BL=1 Code Vector Offset
Reset
Aborted
Power-on reset
1
(asynchronous)
Manual reset
1
—
Reset
H'000 —
—
Reset
H'020 —
H-UDI reset
1
1
Reset
H'000 —
General exception Re-executed User break(before
2
0
Ignored H'1E0 H'00000100
events
instruction execution)
(synchronous)
CPU address error
2
1
Reset
H'0E0 H'00000100
(instruction access) *⁴
*⁵ TLB miss (instruction 2
access) *⁴
1-1
Reset
H'040 H'00000400
TLB invalid
2
(instruction access)*⁴
1-2
Reset
H'040 H'00000100
TLB protection
2
violation
(instruction access)*⁴
1-3
Reset
H'0A0 H'00000100
Illegal general instruction 2
2
Reset
H'180 H'00000100
exception
Illegal slot
2
2
Reset
H'1A0 H'00000100
instruction exception
Completed Unconditional trap
2
4
Reset
H'160 H'00000100
(TRAPA instruction)
Re-executed CPU address error
2
3
Reset
H'0E0/ H'00000100
(data read/write)*⁴
H’100
*⁵ TLB miss (data
2
read/write)*⁴
3-1
Reset
H'040/ H'00000400
H’060
TLB invalid (data
2
read/write)*⁴
3-2
Reset
H'040/ H'00000100
H’060
TLB protection
2
violation (data
read/write)*⁴
3-3
Reset
H'0A0/ H'00000100
H’0C0
Initial page write
2
(data write)*⁴
3-4
Reset
H'080 H'00000100
Completed User breakpoint (After 2
instruction execution,
address)
5
Ignored H'1E0 H'00000100
Rev.1.50 Aug. 30, 2006 Page 163 of 860
REJ09B0288-0150