SH7713 Datasheet, PDF (604/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Initialization
Clear TE and RE bits
in SCSCR to 0
Set TFRST and RFRST bits
in SCFCR to 1
Set CKE1 and CKE0 bits in
SCSCR to B'00 (Internal clock/
SCIFnCK pin is input pin (input
signal is ignored)) (leaving TE,
RE, TIE, and RIE bitscleared to 0)
1. Set the clock selection in SCSCR.
Be sure to clear bits RIE, TIE, TE, and RE
to 0.
2. Set the transfer format in SCSMR.
3. Write a value corresponding to the bit rate
into SCBRR. (Not necessary if an external
clock is used.)
4. Wait at least one bit interval, then set the
TE bit or RE bit in SCSCR to 1. Also set the
RIE, TIE, and REIE bits.
Setting the TE and RE bits enables the TxD
and RxD pins to be used.
Set C/A bit in SCSMR to 0,
and set transfer format
Set value in SCBRR
Wait
1-bit interval elapsed?
No
Yes
Set RTRG1, RTRG0, TTRG1,
and TTRG0 bits in SCFCR.
Clear TFRST and
RFRST bits to 0
Set TE and RE bits in SCSCR to
1, and set RIE, TIE, and REIE bits
End
Figure 16.3 Sample the SCIF Initialization Flowchart
Serial Data Transmission: Figure 16.4 shows a sample flowchart for serial transmission.
Use the following procedure for serial data transmission after enabling the SCIF for transmission.
Rev.1.50 Aug. 30, 2006 Page 564 of 860
REJ09B0288-0150