SH7713 Datasheet, PDF (617/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Serial Data Reception: Figures 16.15 and 16.16 show sample flowcharts for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
To change the operating mode from asynchronous mode to clock synchronous mode without
initialization, be sure to confirm that the flags ORER, PER3 to PER0, and FER3 to FER0 are
cleared to 0.
Initialization
Start reception
Read ORER flag in SCLSR
ORER = 1?
No
Yes
Error handling
Read RDF flag in SCFSR
No
RDF = 1?
Yes
Read receive data from SCFRDR
and clear RDF flag in SCFSR to 0
1. SCIF initialization: See figure 16.3, Sample
SCIF Initialization Flowchart.
2. Receive error handling: If a receive error
occurs, read the ORER flag in SCLSR, then
after executing the necessary error handling,
clear the ORER flag to 0.
Serial reception cannot be continued while the
ORER flag is set to 1.
3. SCIF status check and receive data read:
Read SCFSR, check that the RDF flag is set
to 1, then read receive data in SCFRDR and
clear the RDF flag to 0. Notification that the
RDF flag has changed from 0 to 1 can also
be given by the RXI.
4. Serial reception continuation procedure:
To continue serial reception, read at least the
receive trigger set number of data bytes from
SCFRDR, read 1 from the RDF flag, and then
clear the RDF flag to 0. The number of receive
data in SCFRDR can be ascertained by reading
the lower bits of SCFDR. However, if the DMAC
is activated by the RXI and the value is read from
SCFRDR, the RDF flag is cleared automatically.
No
All data received?
Yes
Clear RE bit in SCSCR to 0
End reception
Figure 16.15 Sample Serial Reception Flowchart
Rev.1.50 Aug. 30, 2006 Page 577 of 860
REJ09B0288-0150