SH7713 Datasheet, PDF (44/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 1 Overview and Pin Function
Peripheral clock (P clock): 33 MHz (max)
• Supports power-down modes:
Sleep mode
Software standby mode
Module standby mode
• A single channel on-chip watch dog timer
Watchdog timer mode and interval timer mode is selectable.
An interrupt can be generated in interval timer mode.
Bus state controller (BSC):
• Physical address space is divided into eight areas: area 0, areas 2 to 4; each a maximum of 64
Mbytes, and areas 5A, 5B, 6A, 6B; each a maximum of 32 Mbytes.
• The following features are settable for each area.
Bus size (8, 16 or 32 bits): The supported bus size differs for each area.
Number of access wait cycles: Numbers of wait-state cycles during reading and writing are
independently selectable for some areas.
Setting of idle wait cycles: For the same area or different area.
Specifying the memory to be connected to each area enables direct connection to SRAM,
SRAM with byte selection, burst ROM (synchronization/asynchronous), SDRAM and
PCMCIA.
• Outputs chip select signal (CS0, CS2 to CS4, CS5A/B, and CS6A/B) for corresponding area
(The CS assert/negate timing can be selected by software.)
Direct memory access controller (DMAC):
• Six channels. Two of these channels (ch0 and ch1) support external requests.
• Supports burst mode and cycle-stealing mode
Timer unit (TMU):
• 3-channel auto reload 32-bit on-chip timer
• 4 types of counter input clocks can be selected
Realtime clock (RTC)*¹:
• On-chip clock, calendar, and alarm
• On-chip 32 kHz crystal oscillator with 1/256-second resolution (interrupt cycle)
Rev.1.50 Aug. 30, 2006 Page 4 of 860
REJ09B0288-0150