SH7713 Datasheet, PDF (632/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
Initial
Bit
Bit Name Value
R/W Description
11
FL3
0
R/W Frame Length
10
FL2
0
R/W 00xx: Slot length is 8 bits and frame length is 8 bits
9
FL1
0
R/W 0100: Slot length is 8 bits and frame length is 16 bits
8
FL0
0
R/W 0101: Slot length is 8 bits and frame length is 32 bits
0110: Slot length is 8 bits and frame length is 64 bits
0111: Slot length is 8 bits and frame length is 128 bits
10xx: Slot length is 16 bits and frame length is 16 bits
1100: Slot length is 16 bits and frame length is 32 bits
1101: Slot length is 16 bits and frame length is 64 bits
1110: Slot length is 16 bits and frame length is 128 bits
1111: Slot length is 16 bits and frame length is 256 bits
Notes: 1. When slot length is specified as 8 bits, control
data cannot be transmitted or received.
2. When LSB is first transmitted or received,
control data cannot be transmitted or received.
x: Don't care
7
TXDIZ 0
R/W High-Impedance Output when Transmission is Invalid
Specifies high-impedance output when transmission is
invalid.
0: High output (1 output) when invalid
1: High-impedance output when invalid
Note: Invalid means when disabled, and when a slot that
is not assigned as transmit data or control data is
being transmitted.
6
LSBF
0
R/W LSB-First Transmission/Reception
Selects the bit order of a transmit/receive frame.
0: MSB-first
1: LSB-first
5
RCIM
0
R/W Receive Control Data Interrupt Mode
Selects the set timing of the RCRDY bit in SISTR.
0: Sets the RCRDY bit in SISTR when the contents of
SIRCR change.
1: Sets the RCRDY bit in SISTR each time when SIRCR
receives control data.
Rev.1.50 Aug. 30, 2006 Page 592 of 860
REJ09B0288-0150