SH7713 Datasheet, PDF (263/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 6 Cache
Virtual address
31
13 12
4 3 210
Entry selection
Longword (LW) selection
Ways 0 to 3
Ways 0 to 3
MMU
0 V U Tag address
1
LW0 LW1 LW2 LW3
511
Physical address
CMP0 CMP1 CMP2 CMP3
Hit signal 1
CMP0: Comparison circuit 0
CMP1: Comparison circuit 1
CMP2: Comparison circuit 2
CMP3: Comparison circuit 3
Figure 6.2 Cache Search Scheme
6.3.2 Read Access
Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. The
LRU is updated to indicate that the hit way is the most recently hit way.
Read Miss: An external bus cycle starts and the entry is updated. The way to be replaced is shown
in table 6.3. Entries are updated in 16-byte units. When the desired instruction or data that caused
the miss is loaded from external memory to the cache, the instruction or data is transferred to the
CPU in parallel with being loaded to the cache. When it is loaded to the cache, the U bit is cleared
to 0 and the V bit is set to 1 to indicate that the hit way is the most recently hit way. When the U
bit for the entry which is to be replaced by entry updating in write-back mode is 1, the cache-
update cycle starts after the entry is transferred to the write-back buffer. After the cache completes
its update cycle, the write-back buffer writes the entry back to the memory. Transfer is in 16-byte
units.
Rev.1.50 Aug. 30, 2006 Page 223 of 860
REJ09B0288-0150