SH7713 Datasheet, PDF (214/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 4 Exception Handling
• Example 2: Repeat loop consisting of three instructions
LDRS
RptDtct + 4 ; [A]
LDRS
RptDtct + 4 ; [A]
SETRC #4
; [A]
RptDtct: RptDtct
; [B] A repeat detection
instruction is an
instruction prior to a
repeat start instruction
RptStart: RptDtct1
; [C1][Repeat start instruction]
RptDtct2
; [C2]
RptEnd: RptDtct3
; [C2][Repeat end instruction]
InstrNext
; [A]
• Example 3: Repeat loop consisting of two instructions
LDRS
RptDtct + 6 ; [A]
LDRS
RptDtct + 4 ; [A]
SETRC #4
; [A]
RptDtct: RptDtct
; [B] A repeat detection
RptStart: RptDtct1
instruction is an
instruction prior to a
repeat start instruction
; [C1][Repeat start instruction]
RptEnd: RptDtct2
; [C2][Repeat end instruction]
InstrNext
; [A]
Rev.1.50 Aug. 30, 2006 Page 174 of 860
REJ09B0288-0150