SH7713 Datasheet, PDF (104/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Instruction
Instruction Code Operation
Privileged
Mode
Cycles T Bit
LDC.L @Rm+,
R4_BANK
0100mmmm11000111 (Rm)→R4_BANK, Rm+4→Rm √
4

LDC.L @Rm+,
R5_BANK
0100mmmm11010111 (Rm)→R5_BANK, Rm+4→Rm √
4

LDC.L @Rm+,
R6_BANK
0100mmmm11100111 (Rm)→R6_BANK, Rm+4→Rm √
4

LDC.L @Rm+,
R7_BANK
0100mmmm11110111 (Rm)→R7_BANK, Rm+4→Rm √
4

LDS Rm,MACH
0100mmmm00001010 Rm→MACH

1

LDS Rm,MACL
0100mmmm00011010 Rm→MACL

1

LDS Rm,PR
0100mmmm00101010 Rm→PR

1

LDS.L @Rm+,MACH 0100mmmm00000110 (Rm)→MACH, Rm+4→Rm

1

LDS.L @Rm+,MACL 0100mmmm00010110 (Rm)→MACL, Rm+4→Rm

1

LDS.L @Rm+,PR
0100mmmm00100110 (Rm)→PR, Rm+4→Rm

1

LDTLB
0000000000111000 PTEH/PTEL→TLB
√
1

NOP
0000000000001001 No operation
–
1

PREF @Rm
0000mmmm10000011 (Rm) → cache
–
1

RTE
0000000000101011
Delayed branch, SSR → SR, √
SPC → PC
5

SETS
0000000001011000 1→S

1

SETT
SLEEP
0000000000011000
0000000000011011
1→T
Sleep

1
1
√
4*¹

STC SR,Rn
0000nnnn00000010 SR→Rn
√
1

STC GBR,Rn
0000nnnn00010010 GBR→Rn

1

STC VBR,Rn
0000nnnn00100010 VBR→Rn
√
1

STC SSR, Rn
0000nnnn00110010 SSR→Rn
√
1

STC SPC,Rn
0000nnnn01000010 SPC→Rn
√
1

STC R0_BANK,Rn 0000nnnn10000010 R0_BANK→Rn
√
1

STC R1_BANK,Rn 0000nnnn10010010 R1_BANK→Rn
√
1

STC R2_BANK,Rn 0000nnnn10100010 R2_BANK→Rn
√
1

STC R3_BANK,Rn 0000nnnn10110010 R3_BANK→Rn
√
1

STC R4_BANK,Rn 0000nnnn11000010 R4_BANK→Rn
√
1

Rev.1.50 Aug. 30, 2006 Page 64 of 860
REJ09B0288-0150