SH7713 Datasheet, PDF (578/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
15 to 8 
All 0
R
Reserved
7
C/A
These bits are always read as 0. The write value
should always be 0.
0
R/W Communication Mode
Selects asynchronous mode or clock synchronous
mode as the SCIF operating mode.
0: Asynchronous mode
1: Clock synchronous mode
6
CHR
0
R/W Character Length
Selects 7 or 8 bits as the asynchronous mode data
length. In clock synchronous mode, a fixed data
length of 8 bits is used regardless of the CHR setting.
0: 8-bit data
1: 7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of
the transmit FIFO data register (SCFTDR) is
not transmitted.
5
PE
0
R/W Parity Enable
In asynchronous mode, selects whether or not parity
bit addition is performed in transmission, and parity
bit checking in reception. In clock synchronous mode,
parity bit addition and checking is not performed,
regardless of the PE bit setting.
0: Parity bit addition and checking disabled
1: Parity bit addition and checking enabled*
Note: * When the PE bit is set to 1, the parity (even or
odd) specified by the O/E bit is added to
transmit data before transmission. In
reception, the parity bit is checked for the
parity (even or odd) specified by the O/E bit.
Rev.1.50 Aug. 30, 2006 Page 538 of 860
REJ09B0288-0150