SH7713 Datasheet, PDF (699/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
Illegal carrier
detection
RX-DV negation
Idle
RE set
Reception
halted
RE reset
Reset
Start of frame
Preamble ^reception
detection
Wait for SFD
reception
SFD
reception
Destination address
Promiscuous and other
reception
station destination address
Own destination address
or broadcast
or multicast
Receivce error
or promiscuous
Error
detection
Data
Error
detection
reception
notification*
Receivce error
detection
End of
reception
Normal reception
Legend
SFD: Start frame delimiter
Note: The error frame also transmits data to the buffer.
CRC
reception
Figure 18.3 EtherC Receiver State Transmissions
1. When the receive enable (RE) bit is set, the receiver enters the receive idle state.
2. When an SFD (start frame delimiter) is detected after a receive packet preamble, the receiver
starts receive processing. Discards a frame with an invalid pattern.
3. In normal mode, if the destination address matches the receiver’s own address, or if broadcast
or multicast transmission or promiscuous mode is specified, the receiver starts data reception.
4. Following data reception from the MII, the receiver carries out a CRC check. The result is
indicated as a status bit in the descriptor after the frame data has been written to memory.
Reports an error status in the case of an abnormality.
5. After one frame has been received, if the receive enable bit is set (RE = 1) in the EtherC mode
register, the receiver prepares to receive the next frame.
Rev.1.50 Aug. 30, 2006 Page 659 of 860
REJ09B0288-0150