SH7713 Datasheet, PDF (577/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.3 Transmit Shift Register (SCTSR)
SCTSR is the register used to transmit serial data.
To perform serial data transmission, the SCIF first transfers transmit data from SCFTDR to
SCTSR, then sends the data sequentially to the TxD pin starting with the LSB (bit 0).
When transmission of one byte is completed, the next transmit data is transferred from SCFTDR
to SCTSR, and transmission started, automatically.
SCTSR cannot be directly read or written to by the CPU.
16.3.4 Transmit FIFO Data Register (SCFTDR)
SCFTDR is an 8-bit 16-stage FIFO data register that stores data for serial transmission.
If SCTSR is empty when transmit data has been written to SCFTDR, the SCIF transfers the
transmit data written in SCFTDR to SCTSR and starts serial transmission.
SCFTDR is a write-only register, and cannot be read by the CPU.
The next data cannot be written when SCFTDR is filled with 16 bytes of transmit data. Data
written in this case is ignored.
The contents of SCFTDR are undefined after a power-on reset or manual reset.
16.3.5 Serial Mode Register (SCSMR)
SCSMR is a 16-bit register used to set the SCIF’s serial communication format and select the
clock source of the baud rate generator.
SCSMR can be read or written to by the CPU at all times.
SCSMR is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby
mode or in the module standby state, and retains its contents.
Rev.1.50 Aug. 30, 2006 Page 537 of 860
REJ09B0288-0150