SH7713 Datasheet, PDF (473/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Figure 12.27 shows the access timing in low-frequency mode. In this mode, commands, addresses,
and write data are output in synchronization with the falling edge of CKIO, which is half a cycle
delayed than the normal timing. Read data is fetched at the rising edge of CKIO, which is half a
cycle faster than the normal timing. This timing allows the hold time of commands, addresses,
write data, and read data to be extended.
If SDRAM is operated at a high frequency with the SLOW bit set to 1, the setup time of
commands, addresses, write data, and read data are not guaranteed. Take the operating frequency
and timing design into consideration when making the SLOW bit setting.
CKIO
CKE
A25 to A0
A12/A11*¹
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*²
Tr
Tc1 Td1
Tde
Tap
Tr
Tc1 Tnop
Trwl
Tap
(High)
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 12.27 Access Timing in Low-Frequency Mode
Power-Down Mode: If the PDOWN bit in SDCR is set to 1, the SDRAM is placed in the power-
down mode by bringing the CKE signal to the low level in the non-access cycle. This power-down
mode can effectively lower the power consumption in the non-access cycle. However, please note
Rev.1.50 Aug. 30, 2006 Page 433 of 860
REJ09B0288-0150