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SH7713 Datasheet, PDF (283/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series | |||
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Section 8 Interrupt Controller (INTC)
Table 8.3 Interrupt Exception Handling Sources and Priority (IRL Mode)
Interrupt Source
Interrupt
Code*1
NMI
Hâ²1C0*2
H-UDI
Hâ²5E0*2
IRL IRL[3:0] = Bâ²0000 Hâ²200*3
IRL[3:0] = Bâ²0001 Hâ²220*3
IRL[3:0] = Bâ²0010 Hâ²240*3
IRL[3:0] = Bâ²0011 Hâ²260*3
IRL[3:0] = Bâ²0100 Hâ²280*3
IRL[3:0] = Bâ²0101 Hâ²2A0*3
IRL[3:0] = Bâ²0110 Hâ²2C0*3
IRL[3:0] = Bâ²0111 Hâ²2E0*3
IRL[3:0] = Bâ²1000 Hâ²300*3
IRL[3:0] = Bâ²1001 Hâ²320*3
IRL[3:0] = Bâ²1010 Hâ²340*3
IRL[3:0] = Bâ²1011 Hâ²360*3
IRL[3:0] = Bâ²1100 Hâ²380*3
IRL[3:0] = Bâ²1101 Hâ²3A0*3
IRL[3:0] = Bâ²1110 Hâ²3C0*3
IRQ IRQ4
Hâ²680*3
IRQ5
Hâ²6A0*3
Interrupt
Priority
Priority
IPR
within IPR Default
(Initial Value) (Bit Numbers) Setting Unit Priority
16


High
15


15


14


13


12


11


10


9


8


7


6


5


4


3


2


1


0 to 15 (0) IPRD (3 to 0) 
0 to 15 (0) IPRD (7 to 4) 
Low
Rev.1.50 Aug. 30, 2006 Page 243 of 860
REJ09B0288-0150
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