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SH7713 Datasheet, PDF (283/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Section 8 Interrupt Controller (INTC)
Table 8.3 Interrupt Exception Handling Sources and Priority (IRL Mode)
Interrupt Source
Interrupt
Code*1
NMI
H′1C0*2
H-UDI
H′5E0*2
IRL IRL[3:0] = B′0000 H′200*3
IRL[3:0] = B′0001 H′220*3
IRL[3:0] = B′0010 H′240*3
IRL[3:0] = B′0011 H′260*3
IRL[3:0] = B′0100 H′280*3
IRL[3:0] = B′0101 H′2A0*3
IRL[3:0] = B′0110 H′2C0*3
IRL[3:0] = B′0111 H′2E0*3
IRL[3:0] = B′1000 H′300*3
IRL[3:0] = B′1001 H′320*3
IRL[3:0] = B′1010 H′340*3
IRL[3:0] = B′1011 H′360*3
IRL[3:0] = B′1100 H′380*3
IRL[3:0] = B′1101 H′3A0*3
IRL[3:0] = B′1110 H′3C0*3
IRQ IRQ4
H′680*3
IRQ5
H′6A0*3
Interrupt
Priority
Priority
IPR
within IPR Default
(Initial Value) (Bit Numbers) Setting Unit Priority
16


High
15


15


14


13


12


11


10


9


8


7


6


5


4


3


2


1


0 to 15 (0) IPRD (3 to 0) 
0 to 15 (0) IPRD (7 to 4) 
Low
Rev.1.50 Aug. 30, 2006 Page 243 of 860
REJ09B0288-0150