SH7713 Datasheet, PDF (165/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
3.5.6 ALU Logical Operations
Figure 3.15 shows the ALU logical operation flow. Table 3.24 shows the variation of this type of
operation. The correspondence between each operand and registers is the same as the ALU fixed-
point operations as shown in table 3.21.
The ALU logical operation is executed between registers. Each source and destination operand is
selected independently from one of the DSP registers. As shown in figure 3.15, this type of
operation uses only the upper word of each operand. The lower word and guard-bit parts are
ignored for the source operand and those of the destination operand are automatically cleared.
These operations are also executed in the DSP stage, as shown in figure 3.10. The DSP stage is the
same stage as the MA stage in which memory access is performed.
39 31
Source 1
0
39 31
0
Source 2
ALU
GT Z N V DC
DSR
Destination
39 31
0
Ignored
Cleared to 0
Figure 3.15 ALU Logical Operation Flow
Table 3.24 Variation of ALU Logical Operations
Mnemonic
PAND
POR
PXOR
Function
Logical AND
Logical OR
Logical exclusive OR
Source 1
Sx
Sx
Sx
Source 2
Sy
Sy
Sy
Destination
Dz
Dz
Dz
Every time an ALU logical operation is executed, the DC, N, Z, V, and GT bits in the DSR
register are basically updated in accordance with the operation result. In case of a conditional
operation, they are not updated even though the specified condition is true and the operation is
executed. In case of an unconditional operation, they are always updated in accordance with the
Rev.1.50 Aug. 30, 2006 Page 125 of 860
REJ09B0288-0150