SH7713 Datasheet, PDF (233/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 5 Memory Management Unit (MMU)
Initial
Bit
Bit Name Value R/W Description
0
AT
0
R/W Address translation
Enables/disables the MMU.
0: MMU disabled
1: MMU enabled
5.3 TLB Functions
5.3.1 Configuration of the TLB
The TLB caches address translation table information located in the external memory. The address
translation table stores the logical page number and the corresponding physical number, the
address space identifier, and the control information for the page, which is the unit of address
translation. Figure 5.6 shows the overall TLB configuration. The TLB is 4-way set associative
with 128 entries. There are 32 entries for each way. Figure 5.7 shows the configuration of virtual
addresses and TLB entries.
Way 0 to 3
Entry 0
Entry 1
VPN(31-17) VPN(11-10) ASID(7-0) V
Way 0 to 3
Entry 0 PPN(28-10) PR(1-0) SZ C D SH
Entry 1
Entry 31
Address Array
Entry 31
Data Array
Figure 5.6 Overall Configuration of the TLB
Rev.1.50 Aug. 30, 2006 Page 193 of 860
REJ09B0288-0150