SH7713 Datasheet, PDF (340/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 10 Power-Down Modes
10.2.2 Standby Control Register 2 (STBCR2)
STBCR2 is an 8-bit readable/writable register that controls the operation of modules in the power-
down mode. This register is initialized to H′00 at power-on reset but retains the previous value
after manual reset.
Bit
Bit Name Initial Value R/W Description
7
MSTP10 0
R/W Module Stop Bit 10
When the MSTP10 bit is set to 1, the supply of the
clock to the H-UDI is halted.
0: H-UDI runs
1: Clock supply to H-UDI halted
6
MSTP9 0
R/W Module Stop Bit 9
When the MSTP9 bit is set to 1, the supply of the
clock to the UBC is halted.
0: UBC runs
1: Clock supply to UBC halted
5
MSTP8 0
R/W Module Stop Bit 8
When the MSTP8 bit is set to 1, the supply of the
clock to the DMAC is halted.
0: DMAC runs
1: Clock supply to DMAC halted
4
MSTP7 0
R/W Module Stop Bit 7
When the MSTP7 bit is set to 1, the supply of the
clock to the DSP is halted.
0: DSP runs
1: Clock supply to DSP halted
3
MSTP6 0
R/W Module Stop Bit 6
When the MSTP6 bit is set to 1, the supply of the
clock to the TLB is halted.
0: TLB runs
1: Clock supply to TLB halted
Rev.1.50 Aug. 30, 2006 Page 300 of 860
REJ09B0288-0150