SH7713 Datasheet, PDF (592/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value
R/W
Description
0
DR
0
R/(W)* Receive Data Ready
In asynchronous mode, indicates that there are
fewer than the receive trigger set number of data
bytes in SCFRDR, and no further data has arrived
for at least 15 etu after the stop bit of the last data
received.
0: Reception is in progress or has ended
successfully and there is no receive data left in
SCFRDR
[Clearing conditions]
• Power-on reset or manual reset
• When all the receive data in SCFRDR has been
read, and 0 is written to DR after reading DR =
1
• When all the receive data in SCFRDR is read by
the DMAC
1: No further receive data has arrived
[Setting condition]
When SCFRDR contains fewer than the receive
trigger set number of receive data bytes, and no
further data has arrived for at least 15 etu after the
stop bit of the last data received*
Note: * Corresponds to 1.5 frame time when the
format of 8-bit length and 1 stop bit is used.
etu: Elementary time unit (time for transfer
of 1 bit)
Note: * Only 0 can be written for clearing the flags.
Rev.1.50 Aug. 30, 2006 Page 552 of 860
REJ09B0288-0150