SH7713 Datasheet, PDF (652/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
17.3.13 Serial Receive Control Data Register (SIRCR)
SIRCR is used to store the SIOF receive control data. SIRCR can be specified only when the FL3
to FL0 bits in SIMDR are specified as 1xxx. SIRCR is initialized by a power-on reset, software
reset, or receive reset.
Bit
31 to 16
Initial
Bit Name Value
SIRC015 to All 0
SIRC00
R/W
R
15 to 0 SIRC115 to All 0 R
SIRC10
Description
Control Channel 0 Receive Data
Store data received from the RXD_SIO pin as control
channel 0 receive data. The position of the control
channel 0 data in the transmission or reception frame is
specified by the CD0A bit in SICDAR.
These bits are valid only when the CD0E bit in SICDAR
is set to 1.
Control Channel 1 Receive Data
Store data received from the RXD_SIO pin as control
channel 1 receive data. The position of the control
channel 1 data in the transmission or reception frame is
specified by the CD1A bit in SICDAR.
These bits are valid only when the CD1E bit in SICDAR
is set to 1.
Rev.1.50 Aug. 30, 2006 Page 612 of 860
REJ09B0288-0150