SH7713 Datasheet, PDF (82/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
2.4 Data Formats
2.4.1 Register Data Format
Register operands are always longwords (32 bits). When the memory operand is only a byte (8
bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register.
31
0
Longword
2.4.2 Memory Data Formats
Memory data formats are classified into byte, word, and longword. Memory can be accessed in
byte, word, and longword. When the memory operand is only a byte (8 bits) or a word (16 bits), it
is sign-extended into a longword when loaded into a register.
An address error will occur if word data starting from an address other than 2n or longword data
starting from an address other than 4n is accessed. In such cases, the data accessed cannot be
guaranteed.
When a word or longword operand is accessed, the byte positions on the memory corresponding to
the word or longword data on the register is determined to the specified endian mode (big endian
or little endian).
Figure 2.7 shows a byte correspondence in big endian mode. In big endian mode, the MSB byte in
the register corresponds to the lowest address in the memory, and the LSB the in the register
corresponds to the highest address. For example, if the contents of the general register R0 is stored
at an address indicated by the general register R1 in longword, the MSB byte of the R0 is stored at
the address indicated by the R1 and the LSB byte of the R1 register is stored at the address
indicated by the (R1 +3).
The on-chip device registers assigned to memory are accessed in big endian mode. Note that the
available access size (byte, word, or long word) differs in each register.
Note: The CPU instruction codes of this LSI must be stored in word units. In big endian mode,
the instruction code must be stored from upper byte to lower byte in this order from the
word boundary of the memory.
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