SH7713 Datasheet, PDF (388/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
18
IWRRS2 0
R/W Idle Cycles for Read-Read in Same Space
17
IWRRS1 1
16
IWRRS0 1
R/W Specify the number of idle cycles to be inserted after the
R/W ^{access to a memory that is connected to the space. The}
target cycle is a read-read cycle of which continuous
accesses are for the same space.
000: No idle cycle inserted
001: 1 idle cycles inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
Rev.1.50 Aug. 30, 2006 Page 348 of 860
REJ09B0288-0150