SH7713 Datasheet, PDF (33/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Figure 24.33 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Bank Active Mode, ACTV + WRITE Commands, TRCD = 1 Cycle,
TRWL = 1 Cycle) ................................................................................................. 814
Figure 24.34 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Bank Active Mode, WRITE Command, Same Row Address, TRCD = 1
Cycle, TRWL = 1 Cycle) ...................................................................................... 815
Figure 24.35 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Bank Active Mode, PRE + ACTV + WRITE Commands,
Different Row Address, TRCD = 1 Cycle, TRWL = 1 Cycle) ............................. 816
Figure 24.36 Synchronous DRAM Auto-Refresh Timing (TRP = 2 Cycle) .............................. 817
Figure 24.37 Synchronous DRAM Self-Refresh Timing (TRP = 2 Cycle) ................................ 818
Figure 24.38 Synchronous DRAM Mode Register Write Timing (TRP = 2 Cycle)................... 819
Figure 24.39 PCMCIA Memory Card Interface Bus Timing ..................................................... 820
Figure 24.40 PCMCIA Memory Card Interface Bus Timing (TED[3:0] = B'0010,
TEH[3:0] = B'0001, One Software Wait, One Hardware Wait)............................ 821
Figure 24.41 PCMCIA I/O Card Interface Bus Timing.............................................................. 822
Figure 24.42 PCMCIA I/O Card Interface Bus Timing (TED[3:0] = B'0010,
TEH[3:0] = B'0001, One Software Wait, One Hardware Wait)............................ 823
Figure 24.43 REFOUT Delay Time ........................................................................................... 823
Figure 24.44 Access Timing in Low-Frequency Mode (Auto Precharge).................................. 825
Figure 24.45 Synchronous DRAM Auto-Refresh Timing
(TRP = 2 Cycle, Low-Frequency Mode) .............................................................. 826
Figure 24.46 Synchronous DRAM Self-Refresh Timing
(TRP = 2 Cycle, Low-Frequency Mode) .............................................................. 827
Figure 24.47 Synchronous DRAM Mode Register Write Timing
(TRP = 2 Cycle, Low-Frequency Mode) .............................................................. 828
Figure 24.48 DREQn Input Timing ............................................................................................ 829
Figure 24.49 TENDn, DACKn Output Timing .......................................................................... 829
Figure 24.50 Oscillation Settling Time when RTC Crystal Oscillator is Turned On ................. 830
Figure 24.51 SCIFnCK Input Clock Timing .............................................................................. 831
Figure 24.52 SCIF Input/Output Timing in Clock Synchronous Mode...................................... 832
Figure 24.53 SIOMCLK Input Timing....................................................................................... 833
Figure 24.54 SIOF Transmit/Receive Timing (Master Mode 1: Fall Sampling Time)............... 833
Figure 24.55 SIOF Transmit/Receive Timing (Master Mode 1: Rise Sampling Time).............. 834
Figure 24.56 SIOF Transmit/Receive Timing (Master Mode 2: Fall Sampling Time)............... 834
Figure 24.57 SIOF Transmit/Receive Timing (Master Mode 2: Rise Sampling Time).............. 835
Figure 24.58 SIOF Transmit/Receive Timing (Slave Mode 1 and Slave Mode 2)..................... 835
Figure 24.59 MII Transmit Timing (Normal Operation) ............................................................ 837
Figure 24.60 MII Transmit Timing (Case of Conflict) ............................................................... 837
Figure 24.61 MII Receive Timing (Normal Operation).............................................................. 838
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