SH7713 Datasheet, PDF (456/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
where the READA command is output to the Td1 cycle where the read data is latched can be
specified for the CS2 and CS3 spaces independently, using the A2CL1 and A2CL0 bits in
CS2WCR or the A3CL1 and A3CL0 bits in CS3WCR and TRCD0 bit in CS3WCR. The number
of cycles from Tc1 to Td1 corresponds to the synchronous DRAM CAS latency. The CAS latency
for the synchronous DRAM is normally defined as up to three cycles. However, the CAS latency
in this LSI can be specified as 1 to 4 cycles. This CAS latency can be achieved by connecting a
latch circuit between this LSI and the synchronous DRAM.
CKIO
A25 to A0
A12/A11*¹
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*²
Td1 Td2
Td3
Td4
Tr
Tc1
Tc2
Tc3
Tc4
Tde
Tap
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 12.14 Burst Read Basic Timing (Auto Precharge)
Rev.1.50 Aug. 30, 2006 Page 416 of 860
REJ09B0288-0150