SH7713 Datasheet, PDF (584/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
1
CKE1
0
R/W Clock Enable 1 and 0
0
CKE0
0
R/W Select the SCIF clock source and enable or disable
clock output from the SCIFnCK pin. The combination
of the CKE1 bit and CKE0 bit determines whether the
SCIFnCK pin is set as a serial clock output pin or a
serial clock input pin. The setting of the CKE0 bit is
available in internal clock operation (CKE1 = 0). In the
case of external clock operation (CKE1 = 1), the
setting of the CKE0 bit is not available. The CKE1
and CKE0 bits must be set before the SCIF operating
mode is selected by SCSMR.
• Asynchronous mode
00: Internal clock/SCIFnCK pin functions as input pin
(input signal ignored)
01: Internal clock/SCIFnCK pin functions as clock
output*²
1-*¹: External clock/SCIFnCK pin functions as clock
input*³
• Clock synchronous mode
00: Internal clock/SCIFnCK pin functions as
synchronous clock output
01: Internal clock/SCIFnCK pin functions as
synchronous clock output
1-*¹: External clock/SCIFnCK pin functions as
synchronous clock input
Notes: 1. When CKE1 = 1, the value of CKE0 is
don't care.
2. The output clock frequency is 16 times the
bit rate.
3. The input clock frequency is 16 times the
bit rate.
Rev.1.50 Aug. 30, 2006 Page 544 of 860
REJ09B0288-0150