SH7713 Datasheet, PDF (448/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Table 12.14 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (3)
Setting
A2/3
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
11 (32 bits) 10 (13 bits) 01 (9 bits)
Output Pin of Row Address Column Address Synchronous
This LSI
Output
Output
DRAM Pin
Function
A17
A26
A17
A16
A25*²
A25*²
A15
A24*²
A24*²
A14 (BA1)
A13 (BA0)
Unused
Specifies bank
A14
A23
A14
A12
Address
A13
A22
A13
A11
A12
A21
L/H*¹
A10/AP
Specifies
address/precharge
A11
A20
A11
A9
Address
A10
A19
A10
A8
A9
A18
A9
A7
A8
A17
A8
A6
A7
A16
A7
A5
A6
A15
A6
A4
A5
A14
A5
A3
A4
A13
A4
A2
A3
A12
A3
A1
A2
A11
A2
A0
A1
A10
A1
Unused
A0
A9
A0
Example of connected memory
512-Mbit product (4 Mwords x 32 bits x 4 banks, column 9 bits product): 1
256-Mbit product (4 Mwords x 16 bits x 4 banks, column 9 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Rev.1.50 Aug. 30, 2006 Page 408 of 860
REJ09B0288-0150