SH7713 Datasheet, PDF (360/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 11 On-Chip Oscillation Circuits
11.4 Register Description
The CPG has the following register. For details on register addresses and register access size, refer
to section 23, List of Registers.
• Frequency control register (FRQCR)
11.4.1 Frequency Control Register (FRQCR)
The frequency control register (FRQCR) is a 16-bit readable/writable register used to specify
whether a clock is output from the CKIO pin, the frequency multiplication ratio of PLL circuit 1,
and the frequency division ratio of the internal clock and the peripheral clock.
Only word access can be used on the FRQCR register. FRQCR is initialized to H’1003 by a
power-on reset, but retains its value in a manual reset and in standby mode.
The write values to bits 15 to 13, 11 to 10, 7 to 6, and 3 should always be 0.
Initial
Bit
Bit Name Value R/W
15 to 13 
All 0
R
12
CKOEN 1
R/W
11

10

0
R
0
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Clock Output Enable
CKOEN specifies whether a clock is output from the
CKIO pin or the CKIO pin is placed in the level-fixed
state in the standby mode, CKIO pin is fixed at low
during STATUS 1 = L, and STATUSO = H, when
CKOEN is set to 0. Therefore, the malfunction of an
external circuit because of an unstable CKIO clock in
releasing the standby mode can be prevented. The
CKIO pin becomes to input pin regardless of the
value of the CKOEN bit in clock operating mode 7.
0: CKIO pin goes to low level state in standby mode.
1: Clock is output from CKIO pin
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev.1.50 Aug. 30, 2006 Page 320 of 860
REJ09B0288-0150