SH7713 Datasheet, PDF (192/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
Instruction Code Fx: 0000
Fx: 0001
Fx: 0010
Fx: 0011 to 1111
MSB
LSB MD: 00
MD: 01
MD: 10
MD: 11
0000 Rn
Rm 11MD MOV. B
@(R0, Rm), Rn
MOV.W @(R0, Rm), MOV.L @(R0, Rm),
Rn
Rn
MAC.L
@Rm+,@Rn+
0001 Rn Rm disp MOV.L Rm,
@(disp:4, Rn)
0010 Rn Rm 00MD MOV.B Rm, @Rn
MOV.W Rm, @Rn MOV.L Rm, @Rn
0010 Rn Rm 01MD MOV.B Rm, @−Rn MOV.W Rm, @−Rn MOV.L Rm, @−Rn DIV0S Rm, Rn
0010 Rn Rm 10MD TST Rm, Rn
AND Rm, Rn
XOR Rm, Rn
OR Rm, Rn
0010 Rn Rm 11MD CMP/STR Rm, Rn XTRCT Rm, Rn
MULU.W Rm, Rn
MULSW Rm, Rn
0011 Rn Rm 00MD CMP/EQ Rm, Rn
CMP/HS Rm, Rn
CMP/GE Rm, Rn
0011 Rn Rm 01MD DIV1 Rm, Rn
DMULU.L Rm,Rn
CMP/HI Rm, Rn
CMP/GT Rm, Rn
0011 Rn Rm 10MD SUB Rm, Rn
SUBC Rm, Rn
SUBV Rm, Rn
0011 Rn Rm 11MD ADD Rm, Rn
DMULS.L Rm,Rn
ADDC Rm, Rn
ADDV Rm, Rn
0100 Rn Fx 0000 SHLL Rn
DT Rn
SHAL Rn
0100 Rn Fx 0001 SHLR Rn
CMP/PZ Rn
SHAR Rn
0100 Rn Fx 0010 STS.L MACH, @−Rn STS.L MACL, @−Rn STS.L PR, @−Rn
0100 Rn 00MD 0011 STC.L SR, @−Rn
STC.L GBR, @−Rn STC.L VBR, @−Rn STC.L SSR, @−Rn
0100 Rn 01MD 0011 STC.L SPC, @−Rn STC.L MOD, @−Rn STC.L RS, @−Rn
STC.L RE, @−Rn
0100 Rn
10MD 0011 STC.L
R0_BANK, @−Rn
STC.L
R1_BANK, @−Rn
STC.L
R2_BANK, @−Rn
STC.L
R3_BANK, @−Rn
0100 Rn
11MD 0011 STC.L
R4_BANK, @−Rn
STC.L
R5_BANK, @−Rn
STC.L
R6_BANK, @−Rn
STC.L
R7_BANK, @−Rn
0100 Rn Fx 0100 ROTL Rn
SETRC Rn
ROTCL Rn
0100 Rn Fx 0101 ROTR Rn
CMP/PL Rn
ROTCR Rn
0100 Rm 00MD 0110 LDS.L
LDS.L @Rm+, MACL LDS.L @Rm+, PR
@Rm+, MACH
0100 Rm 01MD 0110
LDS.L @Rm+, DSR LDS.L @Rm+, A0
0100 Rm 10MD 0110 LDS.L @Rm+, X0 LDS.L @Rm+, X1 LDS.L @Rm+, Y0 LDS.L @Rm+, Y1
Rev.1.50 Aug. 30, 2006 Page 152 of 860
REJ09B0288-0150