SH7713 Datasheet, PDF (208/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 4 Exception Handling
Unconditional trap:
• Conditions
TRAPA instruction executed
• Types
Instruction synchronous, processing-completion type
• Save address
An address of an instruction following TRAPA
• Exception code
H′160
• Remarks
The exception is a processing-completion type, so PC of the instruction after the TRAPA
instruction is saved to SPC. The 8-bit immediate value in the TRAPA instruction is quadrupled
and set in TRA[9:2].
User break point trap:
• Conditions
When a break condition set in the user break controller is satisfied
• Types
Break (L bus) before instruction execution: Instruction synchronous, re-execution type
Operand break (L bus): Instruction synchronous, processing-completion type
Data break (L bus): Instruction asynchronous, processing-completion type
I bus break: Instruction asynchronous, processing-completion type
• Save address
Re-execution type: An address of the instruction where a break occurs (a delayed branch
instruction address if an instruction is assigned to a delay slot)
Processing-completion type: An address of the instruction following the instruction where a
break occurs (a delayed branch instruction destination address if an instruction is assigned to a
delay slot)
• Exception code
H′1E0
• Remarks
For details on the user break controller, refer to section 9, User Break Controller.
Rev.1.50 Aug. 30, 2006 Page 168 of 860
REJ09B0288-0150