SH7713 Datasheet, PDF (527/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Direct Memory Access Controller (DMAC)
DREQ
Bus mastership returned to CPU once
Bus cycle
CPU
CPU CPU DMAC DMAC CPU DMAC DMAC CPU
Read Write
Read Write
Figure 13.9 DMA Transfer Example in Cycle-Steal Mode
(Dual Address, DREQ Low Level Detection)
• Burst Mode
In the burst mode, once the bus mastership is obtained, the transfer is performed continuously
until the transfer end condition is satisfied. In the external request mode with low level
detection of the DREQ pin, however, when the DREQ pin is driven high, the bus passes to the
other bus master after the DMAC transfer request that has already been accepted ends, even if
the transfer end conditions have not been satisfied.
The burst mode cannot be used when the on-chip peripheral module is the transfer request
source. Figure 13.10 shows DMA transfer timing in burst mode.
DREQ
Bus cycle
CPU
CPU CPU DMAC DMAC DMAC DMAC CPU
Read Write Read Write
Figure 13.10 DMA Transfer Example in Burst Mode
(Dual Address, DREQ Low Level Detection)
Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table
13.8 shows the relationship between request modes and bus modes by DMA transfer category.
Rev.1.50 Aug. 30, 2006 Page 487 of 860
REJ09B0288-0150