SH7713 Datasheet, PDF (423/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
12.4.7 Refresh Time Constant Register (RTCOR)
RTCOR is an 8-bit register. When RTCOR matches RTCNT, the CMF bit in RTCSR is set to 1
and RTCNT is cleared to 0.
When the RFSH bit in SDCR is 1, a memory refresh request is issued by this matching signal.
This request is maintained until the refresh operation is performed. If the request is not processed
when the next matching occurs, the previous request is ignored.
If the CMIE bit of the RTCSR is set to 1, an interrupt is requested by this matching signal. This
request is maintained until the CMF bit in RTCSR is cleared to 0. Clearing the CMF bit in RTCSR
affects only interrupts and does not affect refresh requests. This makes it possible to count the
number of refresh requests during refresh by interrupts, and to specify the refresh and interval
timer interrupts simultaneously. When the RTCOR is written, the upper 16 bits of the write data
must be H’A55A to cancel write protection.
Bit
Bit Name
31 to 8 
Initial
Value R/W
All 0 R
7 to 0 
All 0 R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
8-bit Counter
Rev.1.50 Aug. 30, 2006 Page 383 of 860
REJ09B0288-0150